The present invention relates generally to integrated circuits (ICs) and more particularly, to configuring threshold values of counters used in a system on a chip (SoC).
A SoC passes through several stages of production testing before being shipped to a customer. The production testing of the SoC is performed on cycle-accurate automatic test equipment (ATE). The cycle-accurate nature of such testers necessitates transmitting and receiving signals on SoC pads deterministically throughout the chip operation using tester patterns. Failure to meet a predefined timing may lead to undesired yield loss during production runs.
The ATE is programmed to commence various stages of testing of the SoC at predefined times. For example, an ATE that functions based on a clock signal having a predetermined frequency is pre-instructed with a time instant when the desired frequency clock signal will be available for use. The phase locked loops (PLLs) used for generating the desired frequency clock signal require a locking time period to lock the frequency of the clock signal at the desired frequency. Therefore, the ATE has to wait for the locking time period before it can begin using the clock signal to conduct tests on the SoC.
To ensure that the ATE makes the desired frequency clock signal available at identical time instants each time a pattern test cycle is begun, a reset sequence counter is used. The reset sequence counter is configured to provide a wait time before counter expiry. The expiry time period is greater than the PLL locking time period to ensure that subsequent to counter expiry the desired frequency clock signal is available. The expiry of the counter signals availability of the desired frequency clock signal to the ATE, which then initiates a pattern test cycle.
The counters provide a desired wait time by counting a predetermined number of clock cycles of an input clock signal. The input clock signals provided to the counters may have a range of input frequencies, viz. 33 MHz to 167 MHz. The counters are programmed to ensure a minimum wait time irrespective of the input clock signal frequency. For example, for providing a wait time of 100 μs, the counter is configured with a value 0x3FFF, which ensures a wait time of a minimum of 100 μs in a scenario when the highest frequency (167 MHz) input clock signal supported by the counter is used (0x3FFF/167 MHz=100 μs). However, when the lowest frequency clock signal (33 MHz) supported by the counter is used, the wait time becomes approximately 5 times the desired 100 μs wait time (0x3FFF/33 MHz≈500 μs). This results in an undesired delay of 400 μs (500 μs−100 μs=400 μs) in the initiation of the pattern test cycle. The delay introduced in just one pattern translates into a delay of 0.8 s per chip if the chip is tested using 400-500 patterns and each pattern is run at least 4 times (400 μs*500*4=0.8 s). This 0.8 s has an impact on the overall test time of the chip, which in turn has a direct impact on the production cost associated with the chip. Additionally, when the counters are used during a device boot such as for a printer, a mobile phone, etc., this undesirable delay leads to a longer device boot time, which has a direct impact on device performance and customer satisfaction.
Thus, it would be advantageous to be able to set counter values without adding any additional, undesirable delay times that impact device performance.